PO100HSTL11ATU datasheet(1/6 Pages) POTATO

Part #	PO100HSTL11ATU

Description	1 to 2 Differential Clock/Data Fanout Buffer

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Manufacturer	POTATO [Potato Semiconductor Corporation]

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2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer

PO100HSTL11A

1 to 2 Differential Clock/Data Fanout Buffer

02/11/07

1

FEATURES:

Pin Configuration

Logic Block Diagram

Pin Description

DESCRIPTION:

Potato Semiconductor’s PO100HSTL11A is

designed for world top performance using

submicron CMOS technology to achieve 1.24GHz

HSTL output frequency with less than 2.0ns

propagation delay.

The PO100HSTL11A is a low-skew, 1-to-2

differential fanout buffer targeted to meet the

requirements of high-performance clock and data

distribution applications. The device has a fully

differential internal architecture that is optimized

to achieve low signal skews at operating frequen-

cies of up to 1.24GHz .

Vcc

D

GND

Q0

Q1

1

2

3

4

8

7

6

5

D, D

Q0, Q0, Q1, Q1

HSTL Outputs

FUNCTION

LVDS LVPECL HSTL Inputs

VCC

GND

Ground Supply

Positive Supply

Q0

Q1

D

• Patented Technology

• Two HSTL differential outputs

• One pair of LVDS/LVPECL/HSTL/ differential

or single-ended inputs

• Operating frequency up to 1.24GHz with 2pf load

• Operating frequency up to 900MHz with 5pf load

• Operating frequency up to 400MHz with 15pf load

• Very low output pin to pin skew < 40ps

• Propagation delay < 2.0ns max with 15pf load

• 2.4V to 3.6V power supply

• Industrial temperature range: –40°C to 85°C

• Available in 8-pin SOIC package

• Available in 8-pin TSSOP package

Similar Part No. - PO100HSTL11ATU

Manufacturer	Part #	Datasheet	Description
Potato Semiconductor Co...	PO100HSTL179A	692Kb / 8P	Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
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	PO100HSTL179A	1Mb / 7P	High Frequency Noise Canncellation Translator

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