TPS3801J25, TPS3801L30, TPS3801K33, TPS3801I50

ULTRA-SMALL SUPPLY VOLTAGE SUPERVISORS

SLVS219 – AUGUST 1999

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 2.5 V to 6 V IOH = –500 µA

VDD –0.2

VOH

High-level output voltage

VDD = 3.3 V

IOH = –2 mA

VDD –0.4

V

VDD = 6 V

IOH = –4 mA

VDD –0.4

VDD = 2 V to 6 V, IOL = 500 µA

0.2

VOL

Low-level output voltage

VDD = 3.3 V,

IOL = 2 mA

0.4

V

VDD = 6 V,

IOL = 4 mA

0.4

Power-up reset voltage (see Note 2)

VDD ≥ 1.1 V,

IOL = 50 µA

0.2

V

TPS3801J25

2.20

2.25

2.30

VIT

Negative-going input threshold

TPS3801L30

TA 40°Cto+85°C

2.58

2.64

2.70

V

VIT–

gg

g

voltage (see Note 3)

TPS3801K33

TA– 40°C to +85°C

2.87

2.93

2.99

V

TPS3801I50

4.45

4.55

4.65

TPS3801J25

30

Vh

Hysteresis

TPS3801L30

35

mV

Vhys

Hysteresis

TPS3801K33

40

mV

TPS3801I50

60

IIH

High-level input current

MR

MR = 0.7

×VDD,

VDD = 6 V

–40

–60

–100

µA

IIL

Low-level input current

MR

MR = 0 V,

VDD = 6 V

–130

–200

–340

µA

IDD

Supply current

VDD = 2 V,

MR and output unconnected

9

12

µA

IDD

Supply current

VDD = 6 V,

MR and output unconnected

20

25

µA

Ci

Input capacitance

VI = 0 V to VDD

5

pF

NOTES:

2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.

3. To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1

µF ceramic) should be placed near the supply terminals.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t

Pulse width

at VDD

VDD = VIT– + 0.2 V,

VDD = VIT– –0.2 V

3

µs

tw

Pulse width

at MR

VDD ≥ VIT– + 0.2V,

VIL = 0.3 × VDD,

VIH = 0.7 × VDD

100

ns

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td

Delay time

VDD ≥ VIT– + 0.2 V,

MR

≥ 0.7 × VDD

See timing diagram

120

200

280

ms

tPHL

Propagation (delay) time, high-to-low-level

MR to RESET delay

VDD ≥ VIT– + 0.2 V,

VIL = 0.3 × VDD,

VIH = 0.7 × VDD

15

ns

tPHL

output

VDD to RESET delay

VIL =VIT– – 0.2 V,

VIH = VIT– + 0.2 V

1

µs