LV56081GP

No.A1499-6/7

External clock signal startup sequence

VDD

EN

S0

S1

SEL

CLK

Charge pump

(C23)

Regulator

(C23)

SEL=H (External clock)

Do not attempt change the signal after 9.4ms from EN = H

Do not attempt change the signal after 9.4ms from EN = H

Do not attempt change the signal after 9.4ms from EN = H

Set EN = H by setting VDD

at 3V or more

Stop at EN = L or over-current protection

Never set VDD at 3V or less till

the sequence is over (7.5ms after EN = L).

Frequency selection

Frequency selection

External clock selected

Do not attempt change the signal after 9.4ms from EN = H

Do not attempt change the signal after 9.4ms from EN = H

Do not attempt change the signal after 9.4ms from EN = H

Frequency selection

Frequency selection

External clock selected

Frequency selection

Frequency selection

External clock selected

* Internal 1MHz

SEL=L (Internal clock)

* CP clock 1MHz

* CP clock 500kHz

* CP clock 250kHz

* CP clock 125kHz

* CP clock 1/2

φ

* CP clock 1/4

φ

* CP clock 1/8

φ

* CP clock 1/16

φ

* IC internal signal

Internal clock

start at 1MHz

9.4ms (min)

Internal clock

start at 1MHz

9.4ms (min)

Steady operation

Stop

sequence

7.5ms (max)

Steady operation

Stop

sequence

7.5ms (max)

EN Pin and VDD

Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset.

To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more.

Note that operation with VDD and EN pin short-circuited cannot be made.

Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max)

passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence

logic to operate correctly.