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TPS2310 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. TPS2310
Description  DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TPS2310 Datasheet(HTML) 5 Page - Texas Instruments

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TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40
°C < TA < 85°C),
3 V
≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted)
general
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
II(IN1)
Input current, IN1
VI(ENABLE) = 5 V (TPS2311),
0.5
1
mA
II(IN2)
Input current, IN2
VI(ENABLE) = 0 V (TPS2310)
75
200
µA
II(stby)
Standby current (sum of currents into IN1, IN2,
VI(ENABLE) = 0 V (TPS2311)
5
µA
II(stby)
y(
ISENSE1, ISENSE2, ISET1, and ISET2)
VI(ENABLE) = 5 V (TPS2310)
5
µA
GATE1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VG(GATE1_3V)
I
500 nA
VI(IN1) = 3 V
9
11.5
VG(GATE1_4.5V)
Gate voltage
II(GATE1) = 500 nA,
DISCH1 open
VI(IN1) = 4.5 V
10.5
14.5
V
VG(GATE1_10.8V)
DISCH1 oen
VI(IN1) = 10.8 V
16.8
21
VC(GATE1)
Clamping voltage, GATE1
to DISCH1
9
10
12
V
IS(GATE1)
Source current, GATE1
3 V
≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1) + 6 V
10
14
20
µA
Sink current, GATE1
3 V
≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1)
50
75
100
µA
VI(IN1) = 3 V
0.5
tr(GATE1)
Rise time, GATE1
Cg to GND = 1 nF (see Note 2)
VI(IN1) = 4.5 V
0.6
ms
()
g
VI(IN1) = 10.8 V
1
VI(IN1) = 3 V
0.1
tf(GATE)
Fall time, GATE1
Cg to GND = 1 nF (see Note 2)
VI(IN1) = 4.5 V
0.12
ms
()
g
VI(IN1) = 10.8 V
0.2
GATE2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VG(GATE2_3V)
Gate voltage
II(GATE2) = 500 nA DISCH2 open
VI(IN2) = 3 V
9
11.7
V
VG(GATE2_4.5V)
Gate voltage
II(GATE2) = 500 nA, DISCH2 oen
VI(IN2) = 4.5 V
10.5
14.7
V
VC(GATE2)
Clamping voltage,
GATE2 to DISCH2
9
10
12
V
IS(GATE2)
Source current,
GATE2
3 V
≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE2) = VI(IN2) + 6 V
10
14
20
µA
Sink current, GATE2
3 V
≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE2) = VI(IN2)
50
75
100
µA
t (GATE2)
Rise time GATE2
Cg to GND = 1 nF
VI(IN2) = 3 V
0.5
ms
tr(GATE2)
Rise time, GATE2
g
(see Note 2)
VI(IN2) = 4.5 V
VO(VREG) =3V
0.6
ms
tf(GATE2)
Fall time GATE2
Cg to GND = 1 nF
VI(IN2) = 3 V
VO(VREG) = 3 V
0.1
ms
tf(GATE2)
Fall time, GATE2
g
(see Note 2)
VI(IN2) = 4.5 V
0.12
ms
NOTE 2: Specified, but not production tested.


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