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PCS812LIUKF Datasheet(PDF) 2 Page - PulseCore Semiconductor |
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PCS812LIUKF Datasheet(HTML) 2 Page - PulseCore Semiconductor |
2 / 8 page January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 2 of 8 Notice: The information in this document is subject to change without notice. Pin Diagram Pin Description Block Diagram Pin# PCS811 PCS812 Pin Name Description 1 1 GND Ground. 2 2 NC No Connection 3 - RESET RESET is asserted LOW if VCC falls below VTH. RESET remains LOW for atleast 140ms (TRST) once VCC exceeds the Threshold. In addition, RESET is active LOW as long as the manual reset (MR) is low. - 3 RESET RESET is asserted HIGH if VCC falls below VTH. RESET remains HIGH for atleast 140ms (TRST) once VCC exceeds the threshold. In addition, RESET is active HIGH as long as the manual reset (MR) is low. 4 4 MR Manual Reset Input. A logic LOW on MR asserts reset. Reset remains active as long as MR is LOW and for at least 180ms (TMRST) once MR returns HIGH. The active low input has an internal 20k Ω pull-up resistor. The input should be left open if not used. It can be driven by TTL or CMOS logic or shorted to ground by a switch. 5 5 VCC Power supply input voltage (3.0V, 3.3V, 5.0V) 1 2 3 5 4 GND VCC NC RESET (RESET) MR PCS811 (PCS812) RESET Generator Bandgap MR RPULL_UP 20K R1 R2 VCC GND RESET (RESET) |
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