PCS5P23Z05C

May 2007

PCS5P23Z09C

rev 0.1

Zero Cycle Slip Peak EMI Reduction IC

3 of 14

Notice: The information in this document is subject to change without notice.

CLK1

CLK3

1

2

3

5

6

7

8

PCS5P23Z05C

REF

CLK2

GND

CLKOUT

CLK4

4

Spread Spectrum Frequency Generation

The clocks in digital systems are typically square waves

with a 50% duty cycle and as frequencies increase the

edge rates also get faster. Analysis shows that a square

wave is composed of fundamental frequency and

harmonics. The fundamental frequency and harmonics

generate the energy peaks that become the source of

EMI. Regulatory agencies test electronic equipment by

measuring the amount of peak energy radiated from the

equipment. In fact, the peak level allowed decreases as

the frequency increases. The standard methods of

reducing EMI are to use shielding, filtering, multi-layer

PCBs etc. These methods are expensive. Spread

spectrum clocking reduces the peak energy by reducing

the Q factor of the clock. This is done by slowly

modulating the clock frequency. The PCS5P23Z05C/09C

uses the center modulation spread spectrum technique in

which the modulated output frequency varies above and

below the reference frequency

with

a specified

modulation rate. With center modulation, the average

frequency is same as the unmodulated frequency and

there is no performance degradation

Timing-Safe™ technology

Timing-Safe™ technology is the ability to modulate a

clock source with Spread Spectrum technology and

maintain synchronization with any associated data path.

Pin Configuration

S2

2

1

3

4

5

6

7

8

CLKA2

GND

CLKB1

CLKB2

CLKA1

REF

11

9

10

12

13

14

15

16

CLKA3

CLKA4

CLKB3

CLKB4

CLKOUT

GND

PCS5P23Z09C

S1