PCS5P23Z05C

May 2007

PCS5P23Z09C

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Multiple Output Timing-Safe™ Peak EMI reduction IC

General Features

•

Input frequency range:50MHz to 100MHz

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

•

Zero input - output propagation delay

•

Multiple low-skew outputs

•

Output-output skew less than 250pS

•

Device-device skew less than 700pS

•

One input drives 9 outputs, grouped as

4 + 4 + 1(PCS5P23Z09C)

•

One input drives 5 outputs (PCS5P23Z05C)

•

Less than 200 pS cycle-to-cycle jitter

•

Available in 16pin 150-mil SOIC, 4.4 mm TSSOP

(PCS5P23Z09C), and in 8pin 150-mil SOIC,

4.4mm TSSOP package (PCS5P23Z05C)

•

3.3V operation

•

Commercial temperature range

•

Advanced 0.35µ CMOS technology

•

The First True Drop-in Solution

Functional Description

PCS5P23Z05C/09C is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed Timing-Safe™ clocks

with Peak EMI reduction. PCS5P23Z09C accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16-pin package. The PCS5P23Z05C is the

eight-pin version of the PCS5P23Z09C. It accepts one

reference input and drives out five low-skew clocks.

All parts have on-chip PLLs that lock to an input clock on

the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

The PCS5P23Z09C has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. The select input also

allows the input clock to be directly applied to the outputs

for chip and system testing purposes.

Multiple PCS5P23Z05C/09C devices can accept the same

input clock and distribute it. In this case the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output to output skew is

guaranteed to be less than 250pS.

Refer

Table”

for deviations and Input-Output Skew for

PCS5P23Z05C and PCS5P23Z09C devices.

The PCS5P23Z05C/09C is available in two different

package configurations, as shown in the ordering

information table.

Block Diagram

PCS5P23Z09C

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

S2

S1

REF

PLL

CLKOUT

CLK1

CLK2

CLK3

CLK4

PCS5P23Z05C

REF