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PCS5I9658 Datasheet(PDF) 3 Page - PulseCore Semiconductor |
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PCS5I9658 Datasheet(HTML) 3 Page - PulseCore Semiconductor |
3 / 15 page November 2006 PCS5I9658 rev 0.3 3.3V 1:10 LVCMOS PLL Clock Generator 3 of 15 Notice: The information in this document is subject to change without notice. Table 1: Pin Configuration Pin # Pin Name I/O Type Function 6 7 PCLK, PCLK Input LVPECL LVPECL reference clock signal 2 FB_IN Input LVCMOS PLL feedback signal input, connect to QFB 32 VCO_SEL Input LVCMOS Operating frequency range select 3 BYPASS Input LVCMOS PLL and output divider bypass select 4 PLL_EN Input LVCMOS PLL enable/disable 5 MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset 28,26,24, 22,20,18, 16,14,12, 10 Q0-9 Output LVCMOS Clock outputs 30 QFB Output LVCMOS Clock output for PLL feedback, connect to FB_IN 8,9,13,17 21,25,29 GND Supply Ground Negative power supply (GND) 1 VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. 11,15,19, 23,27,31 VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2: Function Table Control Default 0 1 PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. PCS59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the VCO output 1 BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. PCS59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the output dividers. VCO_SEL 1 VCO ÷ 1 (High frequency range). fREF = fQ0-9 =2. fVCO VCO ÷ 2 (Low frequency range). fREF =fQ0-9 =4.fVCO MR/OE 0 Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1. |
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