Custom Clock Generator for Display Systems

2 of 9

April 2007

PCS3P7100A

rev 0.6

Notice: The information in this document is subject to change without notice.

Pin Configuration (6L TSOT- 26 Package)

Pin Description

Pin#

Pin Name

Type

Description

1

CLKIN

I

External Reference Input frequency.

2

VSS

P

Ground to entire chip

3

ModOUT

O

Modulated Frequency Output

4

SS1%

I

Spread Deviation Selection Pin -1. Refer to “Spread Deviation Selection Table”

for details. Has an Internal pull-up resistor.

5

SS2%

I

Spread Deviation Selection Pin -2. Refer to “Spread Deviation Selection Table”

for details. Has an Internal pull-up resistor.

6

VDD

P

Power to entire chip

Spread Deviation Selection Table

SS2% Pin

SS1% Pin

Spread Deviation @ 72MHz

L

L

± 1.50%

L

H

± 1.25%

H

L

± 0.75%

H

H

± 1.00%

VSS

CLKIN

VDD

6

5

4

1

2

3

PCS3P7100A

ModOUT

SS1%

SS2%