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PCS3I625Z0xyG-08-ST Datasheet(PDF) 4 Page - PulseCore Semiconductor |
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PCS3I625Z0xyG-08-ST Datasheet(HTML) 4 Page - PulseCore Semiconductor |
4 / 15 page PCS3P625Z05B/C May 2008 PCS3P625Z09B/C rev 0.1 High Frequency Timing-Safe™ Peak EMI Reduction IC 4 of 15 Notice: The information in this document is subject to change without notice. Pin Configuration for PCS3P625Z09B/C Pin Description for PCS3P625Z09B/C Pin # Pin Name Pin Type Description 1 CLKIN 1 I External reference Clock input, 5V tolerant input 2 CLKOUTA1 2 O Buffered clock Bank A output 4 3 CLKOUTA2 2 O Buffered clock Bank A output 4 4 VDD P 3.3V supply 5 GND P Ground 6 CLKOUTB1 2 O Buffered clock Bank B output 4 7 CLKOUTB2 2 O Buffered clock Bank B output 4 8 S2 3 I Select input, bit 2.See Select Input Decoding table for PCS3P625Z09 for more details 9 S1 3 I Select input, bit 1.See Select Input Decoding table for PCS3P625Z09 for more details 10 CLKOUTB3 2 O Buffered clock Bank B output 4 11 CLKOUTB4 2 O Buffered clock Bank B output 4 12 GND P Ground 13 VDD P 3.3V supply 14 CLKOUTA3 2 O Buffered clock Bank A output 4 15 CLKOUTA4 2 O Buffered clock Bank A output 4 16 DLY_CTRL 2 O External Input-Output Delay control. This pin can be used as clock output Notes: 1. Weak pull down 2. Weak pull-down on all outputs 3. Weak pull-up on these Inputs 4. Buffered clock output is Timing-Safe™ 1 2 3 4 13 14 15 16 PCS3P625Z09B/C 5 6 7 8 9 10 11 12 CLKOUTA3 CLKOUTA4 CLKOUTB3 CLKOUTB4 VDD GND S1 DLY_CTRL VDD GND CLKOUTB1 CLKOUTB2 CLKOUTA1 CLKIN CLKOUTA2 S2 |
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