September 2006

PCS2P5T915A

rev 0.2

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Recommended Operating Range

Symbol

Description

Min

Typ

Max

Unit

Ambient Operating Temperature

-40

+25

+85

° C

1

Internal Power Supply Voltage

2.4

2.5

2.6

V

HSTL Output Power Supply Voltage

1.4

1.5

1.6

V

Extended HSTL and 1.8V LVTTL Output Power Supply Voltage

1.65

1.8

1.95

V

1

2.5V LVTTL Output Power Supply Voltage

V

Termination Voltage

V

Pin Description

Symbol I/O

Type

Description

A

I

Adjustable

1

Clock input. A is the "true" side of the differential clock input. If operating in single-ended

mode, A is the clock input.

I

Adjustable

1

voltage for A:

2.5V LVTTL

1.8V LVTTL, eHSTL

HSTL

LVEPECL

G(+)

I

LVTTL

5

Gate control for "true", Qn, outputs. When G(+)is LOW, the "true" outputs are enabled.

When G(+)is HIGH, the "true" outputs are asynchronously disabled to the level

designated by GL

G(-)

I

LVTTL

5

Gate control for "complementary", Qn, outputs. When G(-)is LOW, the "complementary"

outputs are enabled. When G(-)is HIGH, the "complementary" outputs are

asynchronously disabled to the opposite level as GL

GL

I

LVTTL

5

Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"

outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs

disable HIGH.

Qn

O

Adjustable

2

Clock outputs

Qn

O

Adjustable

2

Complementary clock outputs

RxS

I

3 Level

3

Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential

(LOW) clock input

TxS

I

3 Level

3

Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID)

PWR

Power supply for the device core and inputs

PWR

GND

PWR

Power supply return for all power

Notes: 1. Inputs are capable of translating the following interface standards. User can select between:

Single-ended 2.5V LVTTL levels

Single-ended 1.8V LVTTL levels

or

Differential 2.5V/1.8V LVTTL levels

Differential HSTL and eHSTL levels

Differential LVEPECL levels

4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize

the possibility of runt pulses or be able to tolerate them in down stream circuitry.

5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.