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PCS2I2314ANZ Datasheet(PDF) 7 Page - PulseCore Semiconductor |
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PCS2I2314ANZ Datasheet(HTML) 7 Page - PulseCore Semiconductor |
7 / 13 page September 2006 PCS2I2314ANZ rev 0.5 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs 7 of 13 Notice: The information in this document is subject to change without notice. SDRAM Enable and Disable Times VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load Test Circuit for IIC Rise and Fall Times Figure 3. Test Circuit for IIC RL = 1kΩ CL = 10pF or CL = 400pF VO = 3.3V GND DUT OE INPUT VM VI Figure 2. 3-State Enable and Disable times tPLZ tPZL tPHZ tPZH VM VY VX VM VDD VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL VDD OUTPUT HIGH-to-OFF OFF-to-HIGH Outputs disabled Outputs enabled Outputs enabled GND VSS |
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