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ASM5I23S09AG-1-16-SR Datasheet(PDF) 2 Page - PulseCore Semiconductor

Part # ASM5I23S09AG-1-16-SR
Description  3.3V ?쁓preadTrak??Zero Delay Buffer
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Manufacturer  PULSECORE [PulseCore Semiconductor]
Direct Link  http://www.onsemi.com/
Logo PULSECORE - PulseCore Semiconductor

ASM5I23S09AG-1-16-SR Datasheet(HTML) 2 Page - PulseCore Semiconductor

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ASM5P23S05A
November 2006
ASM5P23S09A
rev 1.5
3.3V ‘SpreadTrak’ Zero Delay Buffer
2 of 18
Notice: The information in this document is subject to change without notice.
Select Input Decoding for ASM5P23S09A
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT
1
Output Source
PLL
Shut-Down
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the
output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
SpreadTrak
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5P23S09A and ASM5P23S05A are designed so as
not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay
buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew
which may cause problems in the systems requiring
synchronization.


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