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TP3064B Datasheet(PDF) 3 Page - Texas Instruments

Part No. TP3064B
Description  MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TP3064B Datasheet(HTML) 3 Page - Texas Instruments

 
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TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D – MAY 1990 –REVISED JULY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
ANLG GND
2
Analog ground. All signals are referenced to ANLG GND.
ANLG LOOP
16
Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit
filter input is disconnected from the output of the transmit preamplifier and connected to the VPO+ output of the
receive power amplifier.
BCLKR/CLKSEL
9
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).
BCLKX
12
The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous
with MCLKX
DR
8
Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX
13
The 3-state PCM data output that is enabled by FSX
FSR
7
Receive frame-sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
FSX
14
Transmit frame-sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
17
Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN
10
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but
should be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected
for all internal timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX
11
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
TSX
15
Open-drain output that pulses low during the encoder time slot
VBB
20
Negative power supply. VBB = – 5 V ± 5%
VCC
6
Positive power supply. VCC = 5 V ± 5%
VFRO
5
Analog output of the receive filter
VFXI+
19
Noninverting input of the transmit input amplifier
VFXI –
18
Inverting input of the transmit input amplifier
VPI
4
Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBB.
VPO+
1
The noninverted output of the receive power amplifier
VPO –
3
The inverted output of the receive power amplifier


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