TMS3473B

PARALLEL DRIVER

SOCS022B – NOVEMBER 1990

5

POST OFFICE BOX 655303

recommended operating conditions (see Note 2)

MIN

NOM

MAX

UNIT

Positive supply voltage, VCC†

0

1

4.4

V

Negative supply voltage, VSS†

–11.1

–10

– 9.7

V

Positive ABG supply voltage, VABG+†

1

3.5

4.4

V

Negative ABG supply voltage, VABG –†

– 11.1

–7

– 6.2

V

Power supply voltage differential (VCC – VSS)

15.5

V

DC parallel image area midlevel voltage, IALVL‡

Z < 5 k

Ω

–6

–5

–2

V

DC antiblooming midlevel voltage, ABLVL

Z < 2.5 k

Ω

– 3.5

– 2.5

1

V

High level input voltage VIH

ABIN, MIDSEL, PD, IAIN, or SAIN

2.5

5

V

High-level input voltage, VIH

I/N

VCC – 0.4

V

Low level input voltage VIL

ABIN, MIDSEL, PD, IAIN, or SAIN

0

0.9

V

Low-level input voltage, VIL

I/N

VSS + 0.4

V

Input voltage VI

ABLVL

– 3.5

1

V

Input voltage, VI

IALVL

–6

–2

V

Frequency f lk

IAIN, SAIN§

3.58

MHz

Frequency, fclock

ABIN§

2

MHz

Input resistance, Ri

IALVL, ABLVL

2.5

k

Ω

Slope-resistance bias

10

50

k

Ω

Input capacitance, Ci

ABLVL

1

µF

Operating free-air temperature, TA

–20

45

°C

† VCC, VSS, VABG+, and VABG– have 100-mA current limits. Adequate decoupling capacitors are required from these terminals to ground.

‡ Proper adjustment is required for interlace-mode operation.

§ Different CCD image sensors have different maximum clock rates. See the individual CCD image sensor data sheets for these rates.