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TMS320VC5402 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320VC5402 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 68 page  TMS320VC5402 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TABLE OF CONTENTS Description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Functions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripherals 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software-Programmable Wait-State Generator 16 . . . . . . . . . Programmable Bank-Switching Wait States 18 . . . . . . . . . . . . Parallel I/O Ports 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced 8-Bit Host-Port Interface 19 . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Ports 20 . . . . . . . . . . . . . . . . . . . . Hardware Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-Mapped Registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Control Registers And Subaddresses 29 . . . . . . . . . . DMA Subbank Addressed Registers 29 . . . . . . . . . . . . . . . . . . Interrupts 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Support 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings 34 . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions 34 . . . . . . . . . . . . . . . . . Electrical Characteristics 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Measurement Information 35 . . . . . . . . . . . . . . . . . . Internal Oscillator With External Crystal 36 . . . . . . . . . . . . . . . . Divide-By-Two Clock Option (PLL Disabled) 37 . . . . . . . . . . . . Multiply-By-N Clock Option 38 . . . . . . . . . . . . . . . . . . . . . . . . . . Memory and Parallel I/O Interface Timing 39 . . . . . . . . . . . . . . Ready Timing For Externally Generated Wait States 45 . . . . . HOLD and HOLDA Timings 49 . . . . . . . . . . . . . . . . . . . . . . . . . . Reset, BIO, Interrupt, and MP/MC Timings 50 . . . . . . . . . . . . . Instruction Acquisition (IAQ), Interrupt Acknowledge (IACK), External Flag (XF), and TOUT Timings 52 . . . . . Multichannel Buffered Serial Port Timing 54 . . . . . . . . . . . . . . . HPI8 Timing 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVISION HISTORY REVISION DATE PRODUCT STATUS HIGHLIGHTS * October 1998 Advanced Information Original A April 1999 Advanced Information Revised to update characteristic data B July 1999 Advanced Information Revised to update characteristic data C September 1999 Advanced Information Revised to update characteristic data D January 2000 Production Data Revised to release production data. E August 2000 Production Data Added Table of Contents, Revision History, and corrected IDLE3 current on page 35. |
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