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TMS320C50 Datasheet(PDF) 56 Page - Texas Instruments |
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TMS320C50 Datasheet(HTML) 56 Page - Texas Instruments |
56 / 91 page TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended operating conditions [ H = 0.5 tc(CO)] (’320LC5x only) (see Figure 14) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 50 75† 40 75† 25 55† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 2 9 16 2 9 16 1 8 15 ns tf(CO) Fall time, CLKOUT1 5 5 4 ns tr(CO) Rise time, CLKOUT1 5 5 4 ns tw(COL) Pulse duration, CLKOUT1 low H–3‡ H H+2‡ H–3‡ H H+2‡ H–3‡ H H+2‡ ns tw(COH) Pulse duration, CLKOUT1 high H–3‡ H H+2‡ H–3‡ H H+2‡ H–3‡ H H+2‡ ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied 1000tc(C2) 1000tc(C2) 1000tc(C2) ns † Clocks can only be stopped while executing IDLE2 when using the PLL clock generator option. ‡ Values assured by design and not tested § On the ’LC56, ’LC57, and ’LC57S devices, CLKIN2 functions as the PLL clock input. |
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