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TMS320C25FNL Datasheet(PDF) 61 Page - Texas Instruments |
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TMS320C25FNL Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 69 page  TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 61 program verify Programmed bits may be verified with VPP = 12.5 V when G = VIL, E = VIL, and PGM = VIH. Figure 11 shows the timing for the program and verify operation. Start Address = First Location VCC = 6 ± 0.25 V VPP = 12.5 V ± 0.25 V X = 0 Program One 1-ms Pulse Verify One Byte Program One Pulse of 3X-ms Duration Last Address? VCC = VPP = 5 V ± 0.25 V Compare All Bytes to Original Data Device Passed X = 25? Device Failed Increment Address No Yes Fail Pass Yes No Fail Pass Increment X Figure 10. Fast Programming Flowchart |
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