TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

4

POST OFFICE BOX 1443

functions

This section lists signal descriptions for the ’320C44 device: each signal, number of pins, operating mode(s)

(that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively ), and function. The signals

are grouped according to function.

Pin Functions

SIGNAL NAME

NO. OF

PINS

TYPE†

DESCRIPTION

GLOBAL-BUS EXTERNAL INTERFACE (73 pins)

D31 – D0

32

I/O/Z

32-bit data port of the global-bus external interface

DE

1

I

Data-bus-enable signal for the global-bus external interface

A23 – A0

24

O/Z

24-bit address port of the global-bus external interface

AE

1

I

Address-bus-enable signal for the global-bus external interface

STAT3 – STAT0

4

O

Status signals for the global-bus external interface

LOCK

1

O

Lock signal for the global-bus external interface

STRB0‡

1

O/Z

Access strobe 0 for the global-bus external interface

R/W0‡

1

O/Z

Read / write signal for STRB0 accesses

PAGE0‡

1

O/Z

Page signal for STRB0 accesses

RDY0‡

1

I

Ready signal for STRB0 accesses

CE0‡

1

I

Control enable for the STRB0, PAGE0, and R / W0 signals

STRB1‡

1

O/Z

Access strobe 1 for the global-bus external interface

R/W1‡

1

O/Z

Read / write signal for STRB1 accesses

PAGE1‡

1

O/Z

Page signal for STRB1 accesses

RDY1‡

1

I

Ready signal for STRB1 accesses

CE1‡

1

I

Control enable for the STRB1, PAGE1, and R / W1 signals

LOCAL-BUS EXTERNAL INTERFACE (73 pins)

LD31 – LD0

32

I/O/Z

32-bit data port of the local-bus external interface

LDE

1

I

Data-bus-enable signal for the local-bus external interface

LA23 – LA0

24

O/Z

24-bit address port of the local-bus external interface

LAE

1

I

Address-bus-enable signal for the local-bus external interface

LSTAT3 – LSTAT0

4

O

Status signals for the local-bus external interface

LLOCK

1

O

Lock signal for the local-bus external interface

LSTRB0‡

1

O/Z

Access strobe 0 for the local-bus external interface

LR / W0

1

O/Z

Read / write signal for LSTRB0 accesses

LPAGE0

1

O/Z

Page signal for LSTRB0 accesses

LRDY0

1

I

Ready signal for LSTRB0 accesses

LCE0

1

I

Control enable for the LSTRB0, LPAGE0, and LR / W0 signals

LSTRB1‡

1

O/Z

Access strobe 1 for the local-bus external interface

LR / W1

1

O/Z

Read / write signal for LSTRB1 accesses

LPAGE1

1

O/Z

Page signal for LSTRB1 accesses

LRDY1

1

I

Ready signal for LSTRB1 accesses

LCE1

1

I

Control enable for the LSTRB1, LPAGE1, and LR / W1 signals

† I = input, O = output, Z = high impedance

‡ The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers.