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TLV5638 Datasheet(PDF) 6 Page - Texas Instruments |
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TLV5638 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 19 page 
TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V –1 µA Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t (FS) Output settling time full scale RL = 10 kΩ,CL = 100 pF, Fast 1 3 µs ts(FS) Output settling time, full scale L , L , See Note 11 Slow 3.5 7 µs t (CC) Output settling time code to code RL = 10 kΩ,CL = 100 pF, Fast 0.5 1.5 µs ts(CC) Output settling time, code to code L , L , See Note 12 Slow 1 2 µs SR Slew rate RL = 10 kΩ,CL = 100 pF, Fast 12 V/ µs SR Slew rate L , L , See Note 13 Slow 1.8 V/ µs Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD 5 nV–s SNR Signal-to-noise ratio 69 74 S/(N+D) Signal-to-noise + distortion fs = 480 kSPS, fout = 1 kHz, 58 67 dB THD Total harmonic distortion s , out , RL = 10 kΩ,CL = 100 pF –69 –57 dB Spurious free dynamic range 57 72 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns twH SCLK pulse width high 25 ns twL SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 10 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns |
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