TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

3

POST OFFICE BOX 655303

detailed description

The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with

256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected

to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use

of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance

of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the

reference source.

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or

times 2 gain.

On power up, the DACs are reset to CODE 0.

Each output voltage is given by:

V

O

(DACA|B|C|D)

+ REF

CODE

256

(1

) RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer

D7

D6

D5

D4

D3

D2

D1

D0

OUTPUT VOLTAGE

0

0

0

0

0

0

0

0

GND

0

0000001

(1/256)

× REF (1+RNG)

•

•••••••

•

•

•••••••

•

0

1111111

(127/256)

× REF (1+RNG)

1

0000000

(128/256)

× REF (1+RNG)

•

•••••••

•

•

•••••••

•

1

1

1

1

1

1

1

1

(255/256)

× REF (1+RNG)

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have

been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as

shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When

LDAC is high during serial programming, the new value is stored within the device and can be transferred to

the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data

transfers using two 8-clock-cycle periods are shown in Figures 3 and 4.

Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output

range. When RNG = low, the output range is between the applied reference voltage and GND, and when

RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

A1

A0

DAC UPDATED

0

0

DACA

0

1

DACB

1

0

DACC

1

1

DACD