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TLV5624 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV5624 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 17 page 
TLV5624 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS235 – JULY 1999 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) reference pin configured as input (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 0 VDD–1.5 V RI Input resistance 10 M Ω CI Input capacitance 5 pF Reference input bandwidth REF=0 2V +1 024Vdc Fast 1.3 MHz Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Slow 525 kHz Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V –1 µA Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t (FS) Output settling time full scale RL = 10 kΩ,CL = 100 pF, Fast 1 3 µs ts(FS) Output settling time, full scale L , L , See Note 11 Slow 3.5 7 µs t (CC) Output settling time code to code RL = 10 kΩ,CL = 100 pF, Fast 0.5 1.5 µs ts(CC) Output settling time, code to code L , L , See Note 12 Slow 1 2 µs SR Slew rate RL = 10 kΩ,CL = 100 pF, Fast 8 V/ µs SR Slew rate L , L , See Note 13 Slow 1.5 V/ µs Glitch energy DIN = 0 to 1, fCLK = 100 kHz, CS = VDD 5 nV–S SNR Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion fs = 480 kSPS, fout = 1 kHz, 48 47 dB THD Total harmonic distortion s , out , RL = 10 kΩ,CL = 100 pF –50 –48 dB Spurious free dynamic range 50 62 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. |
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