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TLV320AIC27IPFB Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AIC27IPFB Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 52 page  TLV320AIC27 STEREO AUDIO CODEC SLAS253 – MARCH 2000 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description 3D stereo enhancement This device contains a stereo-enhancement circuit, designed to optimize the listening experience when the device is used in a typical PC-operating environment (that is, with a pair of speakers placed either side of the monitor with little spatial separation). This circuit creates a differential signal by subtracting left and right channel playback data, then filters this difference signal using low-pass and high-pass filters whose time constants are set using external capacitors connected to the CX3D pins 33 and 34. Typical values of 100 nF and 47 nF set high-pass and low-pass poles at about 100 Hz and 1 kHz respectively. This frequency band corresponds to the range over which the ear is most sensitive to directional effects. The filtered difference signal is gain-adjusted by an amount set using the four-bit value written to register 22h bits 3 to 0. Value 0h is disabled, and value Fh is maximum effect. A typical value of 8h is optimum. The user interface most typically uses a slider type of control to allow the user to adjust the level of enhancement to suit the program material. Bit D13 3D in register 20h is the overall 3D-enable bit. The capability register 00h reads back the value 11000 in bits D14 to D10. This corresponds to decimal 24, which is registered with Intel as Texas Instruments Stereo Enhancement. Note that the external capacitors setting the filtering poles applied to the difference signal can be adjusted in value, or even replaced with a direct connection between the pins. When such adjustments are made, the amount of difference signal fed back into the main signal paths can be significant. This can cause large signals which may limit, distort, or overdrive signal paths or speakers. Adjust these values carefully to select the desired acoustic effect. There is no provision for pseudo-stereo effects. Mono signals have no enhancement applied if they are in phase and have the same amplitude. Signals from the PCM DAC channels do not have stereo enhancement applied. It is assumed that these signals have already been processed digitally with any required 3D-enhancement effect. Applying the analog 3D-enhancement will corrupt the digital effect. This is equivalent to setting the POP bit in register 20h. As a result, the readback value of this bit is fixed as 1, and attempts to change it will be ignored. The POP bit is set to one and cannot be reset. variable sample rate support The DACs and ADCs on this device support all the recommended sample rates specified in the Intel Revision 2.1 specification for both audio and modem rates. Default rates are 48 ksps. If alternative rates are selected, the AC’97 interface continues to run at 48 kw/s (kilowords per second), but data is transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the AC’97 Revision 2.1-compliant controller to ensure that data is supplied to the ac link, and received from the ac link at the appropriate rate. The device supports on-demand sampling. That is, when the DAC signal-processing circuits need another sample a request is sent to the controller, which must respond with a data sample in the next frame it sends. For example, if a rate of 24 ksps is selected, on average the device requests a sample from the controller every other frame, for each of the stereo DACs. Note that if an unsupported rate is written to one of the rate registers, the rate defaults to the nearest rate supported. The register then responds when interrogated with the supported rate the device has defaulted to. |
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