TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 – SEPTEMBER 1998

11

POST OFFICE BOX 655303

sampling/conversion

All of the sampling, conversion, and data output in the device are started by a trigger. This trigger can be the

RD or CSTART signal depending on the mode of conversion and configuration. The falling edge of the RD signal

and the rising edge of the CSTART signal are extremely important since they are used to start the conversion.

These edges need to stay as close to the falling edges of the external clock, if they are used as SYSCLK. The

minimum setup time with respect to the rising edge of the external SYSCLK should be 5 ns minimum. When

the internal SYSCLK is used, this is not an issue, since these two edges start the internal clock automatically;

therefore, the setup time is always met.

USING EXTERNAL CLOCK

S/H Hold Time

ts(TRGL-ECLKH)

Conversion Starts

Next Sampling Starts

td(ECLKL-TRGL)

Conversion Starts

Next Sampling Starts

Sampling Period

VIH

VIL

VIH

VIL

VIH

VIL

EXTERNAL

SYSCLK

RD

CSTART

Figure 8. Conversion Trigger Timing – External Clock

USING INTERNAL CLOCK

td(TRGL-ICLKH)

S/H Hold Time

Conversion Starts

Next Sampling

Starts

Conversion Starts

Next Sampling Starts

VIH

VIL

VIH

VIL

VIH

VIL

RD

CSTART

INTERNAL

SYSCLK

INTERNAL

CLOCK STARTS

Figure 9. Conversion Trigger Timing – Internal Clock