TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 – SEPTEMBER 1998

17

POST OFFICE BOX 655303

mono continuous mode (CR0.(3,2) = 1,0)

The mono continuous mode of conversion is synchronous with the RD signal. Its cycle time is approximately

5 SYSCLK cycles when an external SYSCLK is used (6 SYSCLK cycles when an internal SYSCLK is used).

In the mono continuous mode, the TLV1562 is always sampling the input regardless of the state of other control

signals when it is not in the hold state (the first half SYSCLK cycle after each falling edge of RD). This simplifies

control of the ADC. There is no need to generate any special signal to start the sampling.

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

t c(RD)

t conv1

t (CONV1)

t conv1

t conv1

Hi-Z

CONV 1

CONV 2

CONV 3

t s5

t d(RDL-SAMPLE)

t s2

t s2

t s2

Sample 1

Sample 2

Sample 3

Sample 4

Data 1

Data 2

t en(DATAOUT)

t dis(DATAOUT)

t en(DATAOUT)

t dis(DATAOUT)

Config

CS

WR

RD

DATA

t w(RDL)

t d(CSL-RDL)

Figure 14. Mono Continuous Mode