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TLV1504 Datasheet(PDF) 34 Page - Texas Instruments

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Part No. TLV1504
Description  2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TLV1504 Datasheet(HTML) 34 Page - Texas Instruments

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TLV1504, TLV1508
2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS251 – DECEMBER 1999
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
simplified analog input analysis
Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows.
The capacitance charging voltage is given by:
Vc
+ Vs 1–EXP
–tc
Rt
Ci
Where
Rt = Rs + Zi
tc = Cycle time
(1)
The input impedance Zi is 0.5 k
Ω at 5 V, and is higher (~ 0.6 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
VC (1 2 LSB)
+ VS–
VS
2048
(2)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
Vs–
VS
2048
+ Vs 1–EXP
–tc
Rt
Ci
(3)
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1 2 LSB)
+ Rt
Ci
In(2048)
Where
In(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1 2 LSB)
+ (Rs ) 0.5 kW)
Ci
In(2048)
(4)
This time must be less than the converter sample time shown in the timing diagrams. This is 12
× SCLKs (if the
sampling mode is short normal sampling mode).
tch (1 2 LSB)
v 12
1
f (SCLK)
(5)
Therefore the maximum SCLK frequency is:
max f (SCLK)
+
12
tch 1 2 LSB
+
12
[In(2048)
Rt
Ci]
(6)


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