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TLV1504 Datasheet(PDF) 14 Page - Texas Instruments

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Part No. TLV1504
Description  2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TLV1504 Datasheet(HTML) 14 Page - Texas Instruments

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TLV1504, TLV1508
2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS251 – DECEMBER 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
conversion cycles (continued)
CS
CSTART
SDI
INT
EOC
SDO
Hi-Z
Select/Read
Cycle
Select/Read
Cycle
tsample
tconvert
Previous Conversion
Result
Previous Conversion
Result
FS
Hi-Z
Hi-Z
† This is one of the single shot commands. Conversion starts on next rising edge of CSTART.
Figure 9. Mode 00 Single Shot/Extended Sampling (FS signal used, FS pin connected to TMS320 DSP)
CS used as FS input
When interfacing with the TMS320 DSP using conversion mode 00, the FSR signal from the DSP may be
connected to the CS input if this is the only device on the serial port. This will save one output pin from the DSP.
Output data is made available on the rising edge of SCLK and input data is latched on the rising edge of SCLK
in this case.
modes using the FIFO: modes 01, 10, 11 timing
Modes 01, 10, and 11 timing are very similar except for how and when the FIFO is read, how the device is
configured, and how channel(s) are selected.
Mode 01 (repeat mode) requires a two-cycle configuration where the first one sets the mode and the second
one selects the channel. Once the FIFO is filled up to the threshold programmed, it has the option to either read
the FIFO or configure for other modes. Therefore, the sequence is either configure: select : triggered
conversions : FIFO read : select : triggered conversions : FIFO read or configure : select : triggered conversions
: configure : .... Each configure clears the FIFO and the action that follows the configure command depends on
the mode setting of the device.
NOTE:
When using CSTART to sample in extended mode, the falling edge of the 1st CSTART trigger should
occur no more than 2.5
µs after the falling CS edge (or falling FS edge if FS is active) of the channel
select cycle (see Figure 11).


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