TLC7628C, TLC7628E, TLC7628I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS063A – APRIL 1989 – REVISED MAY 1995

6

POST OFFICE BOX 655303

APPLICATION INFORMATION

8

17

DGND

5

16

15

6

7

14

VDD

WR

CS

DACB

DACA/

DB7

DBO

VI(B)

±10 V

R3 (see Note A)

REFB

8

88

REFA

RFBA

OUTA

AGND

OUTB

RFBA

C1(see Note C)

A1

R4 (see Note A)

C2

(see Note C)

AGND

A3

5 k

Ω

R12

R10

20 k

Ω

(see Note B)

(see

Note B)

R9

10 k

Ω

R8

20 k

Ω

A4

VOB

(see

Note B)

5 k

Ω

R11

10 k

Ω

R7

A2

VOA

20 k

Ω

R5

20 k

Ω

R6 (see Note B)

R2 (see Note A)

R1 (see Note A)

±10 V

VI(A)

RECOMMENDED TRIM

RESISTOR VALUES

R1, R3

R2, R4

500

Ω

150

Ω

Control

Logic

Input

Buffer

Latch

DACA

Latch

DACB

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for VOA = 0 V with

code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.

B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.

C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.

Figure 3. Bipolar Operation (4-Quadrant Operation)

A + 1

A

A8–A15

CPU

8051

WR

ALE

TLC7628

DACA/DACB

CS

WR

DB0

DB7

AD0–AD7

Data Bus

Address Bus

Latch

Address

Decode

Logic

NOTE D: A = decoded address for TLC7628 DACA

A + 1 = decoded address for TLC7628 DACB

Figure 4. TLC7628 — Intel 8051 Interface