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TLC5617ACD Datasheet(PDF) 4 Page - Texas Instruments |
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TLC5617ACD Datasheet(HTML) 4 Page - Texas Instruments |
4 / 20 page TLC5617, TLC5617A PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS151B – JULY 1997 – REVISED MARCH 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref (REFIN)= 2.048 V (unless otherwise noted) static DAC specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 10 bits Integral nonlinearity (INL), end point adjusted Vref(REFIN) = 2.048 V, See Note 1 ±1 LSB Differential nonlinearity (DNL) Vref(REFIN) = 2.048 V, See Note 2 ±0.1 ± 0.5 LSB EZS Zero-scale error (offset error at zero scale) Vref(REFIN) = 2.048 V, See Note 3 ±3 LSB Zero-scale-error temperature coefficient Vref(REFIN) = 2.048 V, See Note 4 3 ppm/ °C EG Gain error Vref(REFIN) = 2.048 V, See Note 5 ±3 LSB Gain error temperature coefficient Vref(REFIN) = 2.048 V, See Note 6 1 ppm/ °C Zero scale Slow 80 PSRR Power-supply rejection ratio Gain See Notes 7 and 8 Slow 80 dB PSRR Power-su ly rejection ratio Zero scale See Notes 7 and 8 Fast 80 dB Gain Fast 80 NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). 5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change. OUT A and OUT B output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Voltage output RL = 10 kΩ 0 VDD –0.4 V Output load regulation accuracy VO(OUT) = 2V, RL from 10 kΩ to 2 kΩ 0.5 LSB IOSC Output short circuit current VO(OUT A) or VO(OUT B) to VDD or AGND 20 mA IO(sink) Output sink current VO(OUT) > 0.25 V 5 mA IO(source) Output source current VO(OUT) < 4.75 V 5 mA reference input (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 0 VDD –2 V Ri Input resistance 10 M Ω Ci Input capacitance 5 pF Reference feedthrough REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) –80 dB Reference input bandwidth (f–3dB) REFIN = 0 2 Vpp +1 024Vdc Slow 0.5 MHz Reference in ut bandwidth (f–3dB) REFIN = 0.2 Vpp + 1.024 V dc Fast 1 MHz NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 00 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at 1 kHz. |
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