TLC2554, TLC2558

5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS220A –JUNE 1999

18

POST OFFICE BOX 655303

FIFO operation

76543210

ADC

12-BIT

×8

FIFO

OD

Serial

FIFO Full

FIFO 3/4 Full

FIFO 1/2 Full

FIFO 1/4 Full

FIFO Threshold Pointer

Figure 15. TLC2554/TLC2558 FIFO

The device has an 8 layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host

after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel

or a series of channels based on a preprogrammed sweep sequence. For example, an application may require

eight measurements from channel 3. In this case, the FIFO is filled with 8 data sequentially taken from channel

3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an orderly

manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0–2–4–6–0–2–4–6 is chosen. An

interrupt is sent to the host as soon as all four data are in the FIFO.

SCLK and conversion speed

should not exceed 10 MHz.

a conversion plus 4 SCLKs overhead.

The devices can operate with an SCLK up to 20 MHz for the supply voltage range specified. The clock

divider provides speed options appropriate for an application where a high speed SCLK is used for faster

I/O. The total conversion time is 14

divide by 2 option produces a {14

× (2/20 M) + 4 × (1/20 MHz)} = 1.6 µs conversion time.

the converter is powered down to save power. The built-in reference is left on in order to quickly resume

operation within one half SCLK period. This provides unlimited choices to trade speed with power savings.

reference voltage

The device has a built-in reference with a level of 4 V. If the internal reference is used, REFP is set to 4 V and

REFM is set to 0 V. An external reference can also be used through two reference input pins, REFP and REFM,

if the reference source is programmed as external. The voltage levels applied to these pins establish the upper

and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values of

REFP, REFM, and the analog input should not exceed the positive supply or be lower than GND consistent with

the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or

higher than REFP and at zero when the input signal is equal to or lower than REFM.