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TLC2551 Datasheet(PDF) 3 Page - Texas Instruments

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Part No. TLC2551
Description  5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TLC2551 Datasheet(HTML) 3 Page - Texas Instruments

 
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TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TLC2551
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN
4
I
Analog input channel
CS
1
I
Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.
CS can be used as the FS pin when a dedicated serial port is used. If TLC2551 is attached to a dedicated DSP serial
port, this terminal can be grounded.
FS
7
I
DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
5
I
Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge.
The output format is MSB first.
When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge
and output data is valid on the falling edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of
FS or the falling edge of CS (whichever happens first). Output data is valid on the falling edge of SCLK. (This is
typically used with an active FS from a DSP).
VDD
6
I
Positive supply voltage
VREF
2
I
External reference input
TLC2552/55
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN0 /AIN(+)
4
I
Analog input channel 0. (positive input for TLV2555)
AIN1/AIN (–)
5
I
Analog input channel 1 (inverted input for TLV2555)
CS/FS
1
I
Chip select/frame sync. A high-to-low transition on the CS/FS removes SDO from 3-state within a maximum delay
time.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
7
I
Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS/FS is
high and presents output data after the CS/FS falling edge until the LSB is presented. The output format is MSB
first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.
VDD
6
I
Positive supply voltage
VREF
2
I
External reference input
detailed description
The TLC2551/2/5 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.


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