THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

11

POST OFFICE BOX 655303

continuous conversion mode

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.

In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running

external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is

written into the FIFO.

Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The

maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case

of a trigger level set to 1 or 4.

Sample N

Channel 1

Sample N+1

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

Sample N+7

Channel 1

Sample N+8

Channel 1

Data N–5

Channel 1

Data N–4

Channel 1

Data N–3

Channel 1

Data N–2

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+1

Channel 1

Data N+2

Channel 1

Data N+3

Channel 1

td(A)

tw(CONV_CLKH)

tw(CONV_CLKL)

tc

td(O)

td(DATA_AV)

td(DATA_AV)

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 1

DATA_AV,

Trigger Level = 4

td(pipe)

50%

50%

Figure 2. Timing of Continuous Conversion Mode (1-channel operation)

Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The

maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows

the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger

level set to 2 or 4.

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 2

DATA_AV,

Trigger Level = 4

Data N–3

Channel 2

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N

Channel 2

Data N+1

Channel 1

Data N+1

Channel 2

td(DATA_AV)

tw(CONV_CLKH)

tw(CONV_CLKL)

td(A)

Sample N

Channel 1,2

Sample N+1

Channel 1,2

Sample N+2

Channel 1,2

Sample N+3

Channel 1,2

Sample N+4

Channel 1,2

tc

td(O)

td(Pipe)

td(DATA_AV)

50%

50%

Figure 3. Timing of Continuous Conversion Mode (2-channel operation)