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THS1206 Datasheet(PDF) 8 Page - Texas Instruments |
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THS1206 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 41 page  THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS217D – MAY 1999 – REVISED APRIL 2000 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, VREF = internal, CL < 30 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA_AV) Delay time 5 ns td(o) Delay time 5 ns tpipe Latency 5 CONV CLK timing specification of the single conversion mode† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tc Clock cycle of the internal clock oscillator 159 167 175 ns tw1 Pulse width, CONVST 1.5 ×tc ns tdA Aperture time 1 ns 1 analog input 2 ×tc ns t2 Time between consecutive start of single conversion 2 analog inputs 3 ×tc ns t2 Time between consecutive start of single conversion 3 analog inputs 4 ×tc ns 4 analog inputs 5 ×tc ns 1 analog input, TL = 1 6 ×tc ns Delay time, DATA_AV becomes active for the trigger 2 analog inputs, TL = 2 7 ×tc ns y, _ gg level condition: TRIG0 = 0, TRIG1 = 0 3 analog inputs, TL = 3 8 ×tc ns 4 analog inputs, TL = 4 9 ×tc ns 1 analog input, TL = 4 3 ×t2 +6×tc ns td(DATA AV) Delay time, DATA_AV becomes active for the trigger 2 analog inputs, TL = 4 t2 +7×tc ns td(DATA_AV) y, _ gg level condition: TRIG0 = 1, TRIG1 = 0 3 analog inputs, TL = 6 t2 +8×tc ns 4 analog inputs, TL = 8 t2 +9×tc ns 1 analog input, TL = 8 7 ×t2 +6×tc ns Delay time, DATA_AV becomes active for the trigger 2 analog inputs, TL = 8 3 ×t2 +7×tc ns y, _ gg level condition: TRIG0 = 0, TRIG1 = 1 3 analog inputs, TL = 9 2 ×t2 +8×tc ns 4 analog inputs, TL = 12 2 ×t2 +9×tc ns D l ti DATA AV b ti f th t i 1 analog input, TL = 14 13 ×t2 +6×tc ns td(DATA_AV) Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 1 TRIG1 = 1 2 analog inputs, TL = 12 5 ×t2 +7×tc ns ( _ ) level condition: TRIG0 = 1, TRIG1 = 1 3 analog inputs, TL = 12 3 ×t2 +8×tc ns † Timing parameters are ensured by design but are not tested. |
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