Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

TCM320AC54 Datasheet(PDF) 3 Page - Texas Instruments

Part No. TCM320AC54
Description  MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
Download  17 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo 

TCM320AC54 Datasheet(HTML) 3 Page - Texas Instruments

 
Zoom Inzoom in Zoom Outzoom out
 3 / 17 page
background image
TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A – NOVEMBER 1994 – REVISED JULY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
ANLG GND
2
Analog ground. All signals are referenced to ANLG GND.
BCLKR/CLKSEL
7
Receive bit (data) clock /clock select terminal for master clock. BCLKR/CLKSEL shifts data into DR after the FSR
leading edge and can vary from 64 kHz to 2.048 MHz. Alternately, BCLKR/CLKSEL can be a logic input that selects
either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in the synchronous mode. BCLKX is used for both
transmit and receive directions (see Table 1).
BCLKX
10
Transmit bit (data) clock. BCLKX shifts out the PCM data on DX and can vary from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
DR
6
Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX
11
The 3-state PCM data output that is enabled by FSX
FSR
5
Frame sync clock input for receive channel. FSR is an 8-kHz pulse train that enables BCLKR to shift PCM data in DR
(see Figures 1 and 2 for timing details).
FSX
12
Frame sync clock input for transmit channel. FSX is an 8-kHz pulse train that enables BCLKX to shift out the PCM
data on DX (see Figures 1 and 2 for timing details).
GSX
14
Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN
8
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). MCLKR/PDN may be synchronous with
MCLKX but should be synchronous with MCLKX for best performance. When the input is continuously low, MCLKX
is selected for all internal timing. When the input is continuously high, the device is powered down.
MCLKX
9
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). MCLKX may be asynchronous with MCLKR.
TSX
13
Transmit time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot.
VBB
1
Negative power supply. VBB = – 5 V ± 10%
VCC
4
Positive power supply. VCC = 5 V ± 10%
VFRO
3
Analog output of the receive filter
VFXI +
16
Noninverting input of the transmit input amplifier
VFXI –
15
Inverting input of the transmit input amplifier


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn