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TCM29C13A Datasheet(PDF) 3 Page - Texas Instruments

Part No. TCM29C13A
Description  COMBINED SINGLE-CHIP PCM CODEC AND FILTER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TCM29C13A Datasheet(HTML) 3 Page - Texas Instruments

 
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TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
NAME
TCM29C13A
TCM129C13A
TCM29C14A
TCM129C14A
TCM29C16A
TCM29C17A
TCM129C16A
TCM129C17A
I/O
DESCRIPTION
ANLG GND
16
20
13
Analog ground return for all internal voice circuits. ANLG GND is
internally connected to DGTL GND.
ANLG IN +
17
21
I
Noninverting analog input to uncommitted transmit operational
amplifier. ANLG IN + is internally connected to ANLG GND on
TCM29C16A, TCM129C16A, TCM29C17A, and TCM129C17A.
ANLG IN –
18
22
14
I
Inverting analog input to uncommitted transmit operational amplifier.
ANLG LOOP
7
I
Provides loopback test capability. When ANLG LOOP is high,
PWRO + is internally connected to ANLG IN.
CLKR
11
13
9
I
Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. CLKR and
CLKX are internally connected together for the TCM29C13A,
TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and
TCM129C17A.
CLKSEL
6
6
I
Clock-frequency selection. CLKSEL must be connected to VBB,
VCC, or GND to reflect the master clock frequency. When tied to VBB,
CLK is 2.048 MHz. When tied to GND, CLK is 1.544 MHz.
When tied to VCC, CLK is 1.536 MHz.
CLKX
11
14
9
I
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. CLKR and
CLKX are internally connected for the TCM29C13A, TCM29C16A,
TCM29C17A, TCM129C13A, TCM129C16A, and TCM129c17A.
DCLKR
7
9
5
I
Selects fixed- or variable-data-rate operation. When DCLKR is
connected to VBB, the device operates in the fixed-data-rate mode.
When DCLKR is not connected to VBB, the device operates in the
variable-data-rate mode and DCLKR becomes the receiver data
clock, which operates at frequencies from 64 kHz to 2.048 MHz.
DGTL GND
10
12
8
Digital ground for all internal logic circuits. DGTL GND is internally
connected to ANLG GND.
FSR/TSRE
9
11
7
I
Frame-synchronization clock input/time-slot enable for receive
channel. In the fixed-data-rate mode, FSR distinguishes between
signaling and nonsignaling frames by a double- or single-length
pulse, respectively. In the variable-data-rate mode, this signal must
remain high for the duration of the time slot. The receive channel
enters the standby state when FSR is TTL low for 300 ms.
FSX/TSXE
12
15
10
I
Frame-synchronization clock input/time-slot enable for transmit
channel. FSX/TSXE operates independently of, but in an analagous
manner to, FSR/TSRE. The transmit channel enters the standby
state when FSX is low for 300 ms.
GSR
4
4
I
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending
upon the voltage at GSR.
GSX
19
23
15
O
Output terminal of internal uncommitted operational amplifier.
Internally, this is the voice signal input to the transmit filter.


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