TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996

19

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

VCC

DGND

VBB

Figure 7. Diode Configuration for Latch-Up Protection Circuitry

internal sequencing

On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for

approximately four frames (500

and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require

approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Valid digital

information, such as on/off hook detection, is available almost immediately, while analog information is available

after some delay.

On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up

To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately

20

µs after an interruption of CLKX. SIGR is held low approximately 20 µs after an interruption of CLKR. These

interruptions could possibly occur with some kind of fault condition.

power-down and standby operations

To minimize power consumption, a power-down mode and three standby modes are provided.

For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled

up to a high logic level and the device remains active. In the power-down mode, the average power consumption

is reduced 15 mW.

Three standby modes give the user the options of placing the entire device on standby, placing only the transmit

channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both

FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is

held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the

entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for

power-down and standby procedures.

Table 1. Power-Down and Standby Procedures

DEVICE STATUS

PROCEDURE

TYPICAL POWER

CONSUMPTION

DIGITAL OUTPUT STATUS

Power down

PDN low

3 mW

TSX and PCM OUT are in the high-impedance state;

SIGR goes low within 10

µs.

Entire device on standby

FSX and FSR are low

3 mW

TSX and PCM OUT are in the high-impedance state;

SIGR goes low within 300 ms.

Only transmit on standby

FSX is low,

FSR is high

40 mW

TSX and PCM OUT are placed in the high-impedance

state within 300 ms.

Only receive on standby

FSR is low,

FSX is high

30 mW

SIGR is placed in the high-impedance state within 300 ms.