SN75LVDS88B

TFT LCD PANEL TIMING CONTROLLER

WITH LVDS INTERFACE

SLLS407 – FEBRUARY 2000

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

functional description

Flatlink

The core of the Flatlink is TIs original 86A LVDS receiver, which has three data channels for the 18-bit color plus

one clock channel.

data alignment

The data alignment block supports dual bus, dual port column driver configuration. When interfacing a 2-port

column driver, the controller arranges pixels in odd and even order, then distributes them to odd and even buses

and each connects to either of the driver ports. Under this setup, the controller outputs one clock, one or two

data polarities (depends on driver), and one inverse ( support line inversion) signal to the drivers.

output formatting

The output formatting provides several functions to reduce EMI, noise, and timing delay arrangement. These

functions are controllable through some optional pins. See the registers and options section for reference.

When enabled this function generates polarity indication signals. This occurs when the number of

transitions in the output data bus exceeds 18-bits compared to the previous output under normal polarity.

The polarity signal will be active and the output will be the opposite polarity to reduce transition.

When enabled, the REV_O and REV_E terminals will output the same line inversion control signals but in

opposite polarities.

timing control

ESP and OSP terminals are used as the horizontal starting pulses output pins. Their outputs are one HCLK

period ahead of the RGB data stream

ECLK and OCLK terminals are responsible for the clock pulses, based on the XGA resolution when its

frequency is at 32.5 MHz.

TP1 and TP2 provide the column driver input latch and output enable signals.

The CPV terminal output the clock pulses to the gate drivers as the horizontal sync timing in its CRT counter

part.

The vertical starting pulse automatically generates at the start of every frame.

The OE1 and OE2 terminals provide the gate output enabale signals.