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SN75FC1000BPHD Datasheet(PDF) 6 Page - Texas Instruments |
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SN75FC1000BPHD Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page SN75FC1000B 1-GIGABIT FIBRE CHANNEL TRANSCEIVER SLLS371 – FEBRUARY 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME NO. TYPE DESCRIPTION POWER VCC _A 20,28,29,53 55,57,59,60 63 Supply Analog power. VCC _A provides a supply reference voltage for the high-speed analog circuits. VCC _CMOS 5,10,23, Supply Digital PECL logic power. VCC _CMOS provides an isolated low-noise power supply for the logic circuits. VCC _RX 50 Supply Receiver power. VCC _RX provides a low-noise supply reference voltage for the receiver high-speed analog circuits. VCC _TTL 42,37 Supply TTL power. VCC _TTL provides a supply reference voltage for the receiver TTL circuits. VCC _TX 18 Supply Transmitter power. VCC _TX provides a low-noise supply reference voltage for the transmitter high-speed analog circuits. GROUND GND_ A 21,32,56,64 Ground Analog ground. GND_A provides a ground reference for the high-speed analog circuits. GND_CMOS 1,14, 25,58 Ground Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits. GND_ RX 51 Ground Receiver ground. GND_ RX provides a ground reference for the receiver circuits. GND_TTL 33,46 Ground TTL circuit ground. GND_TTL provides a ground for TTL interface circuits. GND_TX 15 Ground Transmitter ground. GND_TX provides a ground reference for the transmitter circuits. MISCELLANEOUS RESERVED 26 Reserved. Internally pulled to GND, leave open or assert low. detailed description data transmission The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0 – TD9) on the rising edge of REFCLK (106.25 MHz). The reference clock is also used by the serializer, which multiplies the clock by a factor of 10 providing a 1.0625 Gbaud signal that is fed to the shift register. The data is then transmitted differentially at PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9. transmission latency The data transmission latency of the SN75FC1000B is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. The typical transmission latency is 13 ns. data reception The receiver of the SN75FC1000B deserializes 1.0625 Gbps differential serial data. The 8b/10b data (or equivalent) is retimed based on an extracted clock from the serial data. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with two receive byte clocks (RBC0, RBC1). RBC0 and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered 1.0625 Gbps (531 MHz) clock by 10 providing for two 53-MHz signals. The receiver presents the protocol device byte 0 of the received data valid on the rising edge of RBC1. NOTE: This allows the option of byte alignment without the use of the synchronous detection (SYNC) function by the protocol device. The receiver PLL can lock to the incoming 1.0625 GHz data without the need for a lock-to-reference preset. The received serial data rate (RX+ and RX–) should be 1.0625 Gbps ±0.01% (100 ppm) for proper operation. |
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