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SN754410 Datasheet(PDF) 4 Page - Texas Instruments |
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SN754410 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 7 page SN754410 QUADRUPLE HALF-H DRIVER SLRS007B – NOVEMBER 1986 – REVISED NOVEMBER 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = – 12 mA – 0.9 – 1.5 V IOH = – 0.5 A VCC2 – 1.5 VCC2 – 1.1 VOH High-level output voltage IOH = – 1 A VCC2 –2 V IOH = – 1 A, TJ = 25°C VCC2 – 1.8 VCC2 – 1.4 IOL = 0.5 A 1 1.4 VOL Low-level output voltage IOL = 1 A 2 V IOL = 1 A, TJ = 25°C 1.2 1.8 VO High level output clamp voltage IOK = – 0.5 A VCC2 + 1.4 VCC2 +2 V VOKH High-level output clamp voltage IOK = 1 A VCC2 + 1.9 VCC2 + 2.5 V VO Low level output clamp voltage IOK = 0.5 A – 1.1 –2 V VOKL Low-level output clamp voltage IOK = – 1 A – 1.3 – 2.5 V IOZ( ff) Off-state high-impedance-state VO = VCC2 500 µA IOZ(off) g output current VO = 0 – 500 µA IIH High-level input current VI = 5.5 V 10 µA IIL Low-level input current VI = 0 –10 µA All outputs at high level 38 ICC1 Output supply current IO = 0 All outputs at low level 70 mA All outputs at high impedance 25 All outputs at high level 33 ICC2 Output supply current IO = 0 All outputs at low level 20 mA All outputs at high impedance 5 † All typical values are at VCC1 = 5 V, VCC2 = 24 V, TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 24 V, CL = 30 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td1 Delay time, high-to-low-level output from A input 400 ns td2 Delay time, low-to-high-level output from A input 800 ns tTLH Transition time, low-to-high-level output 300 ns tTHL Transition time, high-to-low-level output See Figure 1 300 ns tr Rise time, pulse input tf Fall time, pulse input tw Pulse duration ten1 Enable time to the high level 700 ns ten2 Enable time to the low level See Figure 2 400 ns tdis1 Disable time from the high level See Figure 2 900 ns tdis2 Disable time from the low level 600 ns |
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