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SN74LVCH32244AGKE Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVCH32244AGKE Datasheet(HTML) 1 Page - Texas Instruments |
1 / 9 page SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS617A – OCTOBER 1998 – REVISED JUNE 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus ™ Family D EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down-Mode Operation D Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D Packaged in Plastic Fine-Pitch Ball Grid Array Package description This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH32244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH32244A is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each 4-bit buffer) INPUTS OUTPUT OE A Y L H H L LL H X Z Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. |
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