SN74LVCH16373A

16BIT TRANSPARENT DTYPE LATCH

WITH 3STATE OUTPUTS

SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003

1

POST OFFICE BOX 655303

Widebus

 Family

Operation

(5-V Input and Output Voltages With

Need for External Pullup/Pulldown

Resistors

JESD 17

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

This 16-bit transparent D-type latch is designed

The SN74LVCH16373A is particularly suitable for

implementing

buffer

registers,

I/O

ports,

bidirectional bus drivers, and working registers. It

can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow

the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP − DL

Tube

SN74LVCH16373ADL

LVCH16373A

SSOP − DL

Tape and reel

SN74LVCH16373ADLR

LVCH16373A

−40

°C to 85°C

TSSOP − DGG

Tape and reel

SN74LVCH16373ADGGR

LVCH16373A

−40

°C to 85°C

TVSOP − DGV

Tape and reel

SN74LVCH16373ADGVR

LDH373A

VFBGA − GQL

Tape and reel

SN74LVCH16373AGQLR

LDH373A

VFBGA − ZQL (Pb-free)

Tape and reel

SN74LVCH16373AZQLR

LDH373A

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

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1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

DGG, DGV, OR DL PACKAGE

(TOP VIEW)