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PE43602 Datasheet(PDF) 7 Page - Peregrine Semiconductor Corp. |
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PE43602 Datasheet(HTML) 7 Page - Peregrine Semiconductor Corp. |
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7 / 11 page  Product Specification PE43602 Page 7 of 11 Document No. 70-0248-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Table 11. Parallel and Direct Interface AC Table 10. Serial Interface AC Characteristics VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Figure 15. Serial Timing Diagram Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram Symbol Parameter Min Max Unit TLEPW Latch Enable minimum pulse width 30 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSIH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns TDIPD Digital register delay (internal, direct mode only) - 5 ns Characteristics VALID T DISU T DIH DI[6:1] LE P/S T PSSU T PSIH T LEPW VALID DO[6:1] T DIPD T PD Symbol Parameter Min. Max. Unit FCLK Serial clock frequency - 10 MHz TCLKH Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - ns TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 - ns TLEPW Latch Enable minimum pulse width 30 - ns TSISU Serial data setup time 10 - ns TSIH Serial data hold time 10 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TASU Address setup time 100 - ns TAH Address hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns D[0] and D[7] must be set to logic low Bits can either be set to logic high or logic low D[0] D[1] D[2] D[3] D[4] D[5] D[7] T SISU T CLKL T LEPW T SIH T CLKH SI CLK LE P/S T LESU T PSSU T PSIH VALID T DISU T PD T DIH D[6] DI[6:1] DO[6:0] |
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