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SN74HSTL16918 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74HSTL16918 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 5 page SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus ™ Family D Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Packaged in Plastic Thin Shrink Small-Outline Package description This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is low, the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken high, the Q outputs are latched at the levels set up at the D inputs. The SN74HSTL16918 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE INPUTS OUTPUT LE D Q L H H L LL H X Q0† † Output level before the indicated steady-state input conditions were established Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Q1 1Q1 GND D1 D2 VCC D3 D4 GND 1LE GND VREF GND 2LE GND D5 D6 D7 VCC D8 D9 GND 2Q9 1Q9 VCC VCC 1Q2 2Q2 GND 1Q3 2Q3 VCC 1Q4 2Q4 GND 1Q5 2Q5 GND 1Q6 2Q6 VCC 1Q7 2Q7 GND 1Q8 2Q8 VCC VCC |
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