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LTC2222 Datasheet(PDF) 21 Page - Linear Technology

Part # LTC2222
Description  12-Bit,105Msps/80Msps ADCs
Download  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2222 Datasheet(HTML) 21 Page - Linear Technology

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LTC2222/LTC2223
21
22223fa
APPLICATIO S I FOR ATIO
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2222/LTC2223 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
The lower limit of the LTC2222/LTC2223 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2222/LTC2223 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Figure 13. Digital Output Buffer
LTC2222/LTC2223
22223 F13
OVDD
VDD
VDD
0.1
µF
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Table 1. Output Codes vs Input Voltage
AIN
+ – AIN–
D11 – D0
D11 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
1111 1111 1111
0111 1111 1111
+0.999512V
0
1111 1111 1111
0111 1111 1111
+0.999024V
0
1111 1111 1110
0111 1111 1110
+0.000488V
0
1000 0000 0001
0000 0000 0001
0.000000V
0
1000 0000 0000
0000 0000 0000
–0.000488V
0
0111 1111 1111
1111 1111 1111
–0.000976V
0
0111 1111 1110
1111 1111 1110
–0.999512V
0
0000 0000 0001
1000 0000 0001
–1.000000V
0
0000 0000 0000
1000 0000 0000
<–1.000000V
1
0000 0000 0000
1000 0000 0000
22223 F09a
ENC
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
µF
LTC2222/
LTC2223
22223 F09b
ENC
ENC+
130
3.3V
3.3V
130
D0
Q0
Q0
MC100LVELT22
LTC2222/
LTC2223
83
83


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