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LTC2217CUP Datasheet(PDF) 7 Page - Linear Technology |
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LTC2217CUP Datasheet(HTML) 7 Page - Linear Technology |
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7 / 32 page  LTC2217 7 2217f TIMING DIAGRAM Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz, LVDS outputs, differential ENC+/ ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.75VP-P with differential drive, unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tH tD tC tL N – 7 N – 6 N – 5 N – 4 N – 3 ANALOG INPUT ENC– ENC+ CLKOUT – CLKOUT+ D0-D15, OF 2217 TD01 tAP N + 1 N + 2 N + 4 N + 3 N ELECTRICAL CHARACTERISTICS |
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