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SN74ALVC7805 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN74ALVC7805
Description  256 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74ALVC7805 Datasheet(HTML) 1 Page - Texas Instruments

 
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SN74ALVC7805
256
× 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
™ Family
D Low-Power Advanced CMOS Technology
D Operates From 3-V to 3.6-V VCC
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D Read and Write Operations Synchronized
to Independent System Clocks
D Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
D Bidirectional Configuration and Width
Expansion Without Additional Logic
D Input-Ready Flag Synchronized to Write
Clock
D Output-Ready Flag Synchronized to Read
Clock
D Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D Data Rates up to 50 MHz
D Pin-to-Pin Compatible With SN74ACT7803,
SN74ACT7805, and SN74ACT7813
D Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Lead Spacing
description
The SN74ALVC7805 is suited for buffering
asynchronous data paths up to 50-MHz clock
rates and 13-ns access times. This device is
designed for 3-V to 3.6-V VCC operation. Two
devices can be configured for bidirectional data
buffering without additional logic.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO
must be reset upon power up.
The SN74ALVC7805 is characterized for operation from 0
°C to 70°C.
Copyright
© 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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RESET
D17
D16
D15
D14
D13
D12
D11
D10
VCC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
IR
OE1
Q17
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
VCC
Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR
DL PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.


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