125M/1.25G Spring-Latch SFP Transceiver

10km transmission

Preliminary Datasheet

Oct. 15, 2006

Fiberxon Proprietary and Confidential, Do Not Copy or Distribute

Page 8 of 10

board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; logic 1 indicates a

laser fault of some kind. In the low state, the output will be pulled to less than 0.8V.

2. TX Disable is an input that is used to shut down the transmitter optical output. It is pulled up within the

module with a 4.7k~10k

Ω resistor. Its states are:

Low (0~0.8V):

Transmitter on

(>0.8V, <2.0V):

Undefined

High (2.0~3.465V):

Transmitter Disabled

Open:

Transmitter Disabled

3. MOD-DEF 0,1,2 are the module definition pins. They should be pulled up with a 4.7k~10k

Ω resistor on

the host board. The pull-up voltage shall be VccT or VccR.

MOD-DEF 0 is grounded by the module to indicate that the module is present

MOD-DEF 1 is the clock line of two wire serial interface for serial ID

MOD-DEF 2 is the data line of two wire serial interface for serial ID

4. LOS is an open collector output, which should be pulled up with a 4.7k~10k

Ω resistor on the host board to

a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.

In the low state, the output will be pulled to less than 0.8V.

5. These are the differential receiver output. They are internally AC-coupled 100Ω differential lines which

should be terminated with 100Ω (differential) at host with SGMII interface.

6. These are the differential transmitter inputs. They are AC-coupled, differential lines with 100Ω differential

termination inside the module.

7. When hardware rate selection has higher priority than software configuration via I2C, this pin can be used

to select bit rate by host hardware.

SGMII Interface

SGMII uses two data signals and two clock signals to convey frame data and link rate information between a

100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625

MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair

thus providing signal integrity while minimizing system noise.

However, specific implementations may desire to recover clock from the data rather than use the supplied

clock, such as in our transceiver design. This operation is allowed.

Clearly, SGMII’s 1.25 Gbaud transfer rate is excessive for interfaces operating at 100 Mbps. When these

situations occur, the interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbps.

This frame elongation takes place “above” the 802.3z PCS layer, thus the start frame delimiter only appears

once per frame.The 802.3z PCS layer may remove the first byte of the “elongated” frame.

For further information about how to use transceivers with SGMII interface, please refer to the application note

of FTM-3413C-SLCG

Mechanical Design Diagram

The mechanical design diagram is shown in Figure 4.