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SN65LVDS95DGG Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDS95DGG Datasheet(HTML) 7 Page - Texas Instruments |
7 / 13 page SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION 0 V YP YM VID 49.9 Ω ±1% (2 Places) VOC CL = 10 pF MAX (2 Places) VOD(L) VOD(H) VOC(PP) 0 V VOC(SS) VOC(SS) tf tr 100% 80% 20% 0% NOTE: The lumped instrumentation capacitance for any single ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output shall be similarly loaded. Figure 3. Test Load and Voltage Definitions for LVDS Outputs CLKIN EVEN Dn ODD Dn T VIH = 2 V and VIL = 0.8 V Figure 4. Worst-Case‡ Power Test Pattern ‡ The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs. |
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