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SN65LVDS95DGG Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LVDS95DGG Datasheet(HTML) 5 Page - Texas Instruments |
5 / 13 page SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT Input voltage threshold 1.4 V |VOD| Differential steady-state output voltage magnitude 247 454 ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states RL = 100 Ω, See Figure 3 50 mV VOC(SS) Steady-state common-mode output voltage See Figure 3 1.125 1.375 V VOC(PP) Peak-to-peak common-mode output voltage See Figure 3 80 150 mV IIH High-level input current VIH = VCC 20 µA IIL Low-level input current VIL = 0 V ±10 µA IOS Short circuit output current VOY = 0 V ±24 mA IOS Short-circuit output current VOD = 0 V ±12 mA IOZ High-impedance state output current VO = 0 V to VCC ±10 µA Disabled, all inputs at GND 280 µA ICC(AVG) Quiescent current (average) Enabled, RL = 100 Ω (4 places), Worst-case pattern (see Figure 4), tc = 15.38 ns 85 110 mA Ci Input capacitance 3 pF † All typical values are VCC = 3.3 V, TA = 25°C. timing requirements MIN NOM MAX UNIT tc Input clock period 15.4 tc 50 ns tw High-level input clock pulse width duration 0.4tc 0.6tc ns tt Input signal transition time 5 ns tsu Data setup time, D0 through D27 before CLKIN ↑ (’95) (see Figure 2) 3 ns th Data hold time, D0 through D27 after CLKIN ↑ (’95) (see Figure 2) 1.5 ns |
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