SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

7

POST OFFICE BOX 655303

SN55LVDS31 electrical characteristics over recommended operating conditions (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN55LVDS31

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOD

Differential output voltage magnitude

247

340

454

mV

∆VOD

Change in differential output voltage magnitude

between logic states

RL = 100 Ω,

See Figure 2

–50

50

mV

VOC(SS)

Steady-state common-mode output voltage

1.125

1.2

1.375

V

∆VOC(SS)

Change in steady-state common-mode output voltage

between logic states

See Figure 3

–50

50

mV

VOC(PP)

Peak-to-peak common-mode output voltage

50

150

mV

VI = 0.8 V or 2 V,

No load

Enabled,

9

20

mA

ICC

Supply current

VI = 0.8 or 2 V,

Enabled

RL = 100 Ω,

25

35

mA

VI = 0 or VCC,

Disabled

0.25

1

mA

IIH

High-level input current

VIH = 2

4

20

µA

IIL

Low-level input current

VIL = 0.8 V

0.1

10

µA

IOS

Short circuit output current

VO(Y) or VO(Z) = 0

–4

–24

mA

IOS

Short-circuit output current

VOD = 0

±12

mA

IOZ

High-impedance output current

VO = 0 or 2.4 V

±1

µA

IO(OFF)

Power-off output current

VCC = 0,

VO = 2.4 V

±4

µA

CI

Input capacitance

3

pF

† All typical values are at TA = 25°C and with VCC = 3.3 V.

SN55LVDS31 switching characteristics over recommended operating conditions (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN55LVDS31

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tpLH

Propagation delay time, low-to-high-level output

0.5

1.4

4

ns

tpHL

Propagation delay time, high-to-low-level output

1

1.7

4.5

ns

tr

Differential output signal rise time (20% to 80%)

RL = 100 Ω,

CL = 10 pF,

0.4

0.5

1

ns

tf

Differential output signal fall time (80% to 20%)

L

,

L

,

See Figure 2

0.4

0.5

1

ns

tsk(p)

Pulse skew (|tPHL – tPLH|)

0.3

0.6

ns

tsk(o)

Channel-to-channel output skew‡

0.3

0.6

ns

tpZH

Propagation delay time, high-impedance-to-high-level output

5.4

15

ns

tpZL

Propagation delay time, high-impedance-to-low-level output

See Figure 4

2.5

15

ns

tpHZ

Propagation delay time, high-level-to-high-impedance output

See Figure 4

8.1

17

ns

tpLZ

Propagation delay time, low-level-to-high-impedance output

7.3

15

ns

† All typical values are at TA = 25°C and with VCC = 3.3 V.

‡ tsk(o) is the maximum delay time difference between drivers on the same device.